The XOR sequence locks up on 0, and the XNOR sequence locks up on 255. It is the XOR sequence which ranges from 1 to 255. Contrary to the note I pasted into the schematic I sent you in an earlier reply, the XNOR sequence ranges from 0 to 254 instead of 1 to 255 as I noted. The XNOR count sequence will not hang in this situation. The reason that I chose to use an XNOR in the feedback path is that the system reset pulse will clear the shift register, and with an XOR feedback, the counter will not count: 0 XOR 0 => 0. When it is high, the shift register will count in accordance with an XNOR count sequence, and when it's low, it will count in accordance with an XOR count sequence. The counter will count in two different sequences as the shift register clock rising edge hits on a 2.4576 MHz high or low. ![]() However, I suspect that there will be a fair interaction between the two clocks because the half period of the 2.4576 MHz clock (203 ns) is not greater than the period of the 4 MHz clock (250ns). Apart from the obvious periodic metastable condition that will occur whenever the high pulse of the 2.4756 MHz clock violates the setup/hold time of the shift register's 4 MHz clock, an unpredictable pseudo-random count will be the result of your suggested modification and that effect may be perfectly acceptable.
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